1. Field of the Invention
This invention relates to semiconductor packaging technology, and more particularly, to a semiconductor device with reinforced under-support structure and method of fabricating the same, which can be used in the fabrication of a semiconductor device, such as a MPBGA (Multi-Package Ball Grid Array) device having at least one TFBGA (Thin Fine-pitch Ball Grid Array) package to help reinforce the TFBGA package's under-support structure and thereby prevent the TFBGA package against stress damage, or can be used in the fabrication of a semiconductor device having a flip-chip structure to reinforce the flip-chip structure.
2. Description of Related Art
MPBGA (Multi-Package Ball Grid Array) is an advanced type of semiconductor device packaging technology, which can be used to pack two or more packages on one single substrate, so as to allow one single semiconductor device to offer a manifold level of functionality or data storage capacity. A graphic control unit, for instance, is typically designed in such a manner as to include a graphic control chip package together with one or more memory chip packages on the same substrate, so as to allow one semiconductor device to offer all the required graphic control functionality without having to be attached to external memory modules.
FIGS. 1A–1B are schematic diagrams showing the architecture of a conventional MPBGA semiconductor device. As shown, this MPBGA semiconductor device is constructed on a substrate 100 for the packaging of three packages: a first package 110, a second package 120, and a third package 130, wherein the first package 110 and the second package 120 are each, for example, a TFBGA (Thin Fine-pitch Ball Grid Array) type of memory chip package, while the third package 130 is for example a graphic control chip package. In this MPBGA semiconductor device, the first package 110 and the second package 120 are mounted on the substrate 100 by means of an array of solder bumps 111 (FIG. 1B only shows the under-support structure of the first package 110). By contrast, the third package 130 is electrically connected to the substrate 100 by means of bonding wires 131 and further encapsulated in a molded encapsulation body 132. Finally, the MPBGA semi-conductor device is mounted by means of solder balls 140 (i.e., ball grid array) to an external printed circuit board 150.
As the first package 110 and the second package 120 are bonded in position over the substrate 100, however, a gap would be undesirably left between each TFBGA package (FIG. 1B only shows the first package 110) and its underlying surface, which, if not underfilled, would easily cause the under-support structure to suffer from fatigue cracking and electrical failure due to thermal stress when the entire semiconductor device is being subjected to high-temperature conditions. As a solution to this problem, it is an essential step in the fabrication process to fill an underfill material, such as epoxy resin, into the under-package gap to form an underfill layer 112 which, when hardened, can serve as a mechanical reinforcement for the under-support structure of the first package 110 to cope against thermal stress.
One drawback to the fabrication of the underfill layer 112, however, is that it would require a highly complex process to achieve, which is quite laborious and time-consuming, making the overall packaging process quite cost-ineffective.
Related art includes, for example, the following patents:                U.S. Pat. No. 6,020,633 “INTEGRATED CIRCUIT PACKAGED FOR RECEIVING ANOTHER INTEGRATED CIRCUIT”;        U.S. Pat. No. 5,381,307 “SELF-ALIGNING ELECTRICAL CONTACT ARRAY”; and        Japanese Patent JP 11111768 “MANUFACTURE OF SEMICONDUCTOR DEVICE”.        
The U.S. Pat. No. 6,020,633 discloses a special type of MPBGA module structure. One drawback to this patent, however, is that it still utilizes under-fill technology to form an underfill layer for reinforcing the under-support structure of the TFBGA package on the substrate, so that it still has the above-mentioned drawbacks of the underfill method.
The U.S. Pat. No. 5,381,307 discloses the use of a specially-designed solder-pad array that includes large-size solder balls at the corners thereof to help align the package in position during reflow process, and can additionally help reinforce under-support structure. One drawback to this patent, however, is that it requires an increase in the number of pads on the substrate, thus undesirably making the overall layout design work more complex and laborious to implement. In addition, for TFBGA (Thin Fine-pitch Ball Grid Array) packages whose ball pitch thereof is below 0.75 mm, the provision of large-size solder balls at corners requires the solder balls to be laid at different ball pitches to prevent these solder balls to come in touch with each other and result in the bridging therebetween.
Japanese Patent JP 11111768 discloses a semiconductor device fabrication method that is characterized by the application of an adhesive agent at the corners to help reinforce under-support structure. One drawback to this solution, however, is that it requires a complex process to implement and is thus quite cost-ineffective.
There exists therefore a need for a new semiconductor device packaging technology that can help reinforce under-support structure without having to use underfill technology for the purpose of allowing the overall fabrication process to be more simplified and cost-effective to implement.